PlayStation Vita Architecture (Part 1)

A rapid introduction

The PSVita is a remarkworthy intersection between the video-game set upment and the rapidly evolving mobile sector. Times have alterd, and it won’t be basic for Sony as it faces fierce competition from inexpensive gadgets that do more than fair create phone calls.

The new analysis of this series dives into the contransient technology behind Sony’s new deinhabitry. Do predict to discover recognisable circuitry – perhaps too understandn. Even so, Sony made evident efforts to steer away from any resemblance to the cleverphone labelet.

Models and variants

As the console sat on store shelves, Sony revisited its product strategy multiple times, directing to three variants of the PSVita being shipped thcdisesteemfulout its lifecycle:

• The innovative PSVita (sometimes called the ‘Fat’ model) is the series debut.
• The Slim revision retains the same architecture, but trades the OLED screen for an LCD to shrink costs. Furthermore, it doesn’t advise a 3G-able variant anymore. It does, however, feature a bigger eMMC chip… only 52 MB bigr! For some strange reason, that was enough to provide an inner 1 GB memory card. In any case, I’ll elucidate more in the ‘Games’ section.
• The PlayStation TV is fair a Slim motherboard altered for the non-portable setting.

As you can see, the increateation in this article will easily utilize to all three models, although I will dedicate extra paragraphs to talk about the puzzling eMMC alters of the last two variants.

A new publishing model

Until now, my deinhabitry model participated finishing the whole analysis and then publishing a finish article at once. However, as I persist studying the 8th generation, my articles have ponderably lengthenn in intricateity. They tfinish to get almost a year to finish, and the scrutinize process has become too cumbersome. Thus, for a alter, I’d enjoy to try a new phased approach where I publish by sections instead, begining with the CPU. This will also create the scrutinizeing stage more effective.

Having shelp that, let’s begin with the first section.

CPU

Sony had been an avid adselecter of MIPS technology since the innovative PlayStation. Even at times when SGI/MIPS was losing labelet split in the procrastinateed 90s, Sony shipped a prosperous product carrying MIPS’ revamped line. However, the next decade showd sour: ARM regulated to monopolise the mobile labelet and MIPS’ adselection only unreasonableinished. Thus, Sony ultimately put their faith in an ARM CPU instead, and Toshiba (Sony’s seal manufacturing partner) would now join the role of ARM licensee.

The resulting motherboard only hoparticipates a handful of fused circuits, but they package a fuse of schedules authored by contrastent companies. The main chip is called Kermit ^[1] (a name borrowed from ‘The Muppets’), it features the bigst amount of circuitry, and it’s where the main CPU lives.

Now, while Kermit is pondered a System-On-Chip (SoC), it exceptionpartner regulates to fuse big amounts of memory and processors wiskinny the same package. This is thanks to Toshiba’s Stacked Chip SoC (SCS) lie model ^[2]. Wiskinny it, circuitry is piled on top of others – as resistd to being externpartner combineed side-by-side. The honest consequence is an increase of prohibitdwidth and a reduction of surface footprint, at the cost of a more intricate heat dissipation schedule.

In any case, SCS lie assistd Sony and Toshiba to fit cutting-edge technology while protecting an energy-effective profile, fair see at all the components Kermit hoparticipates:

• The main CPU, a quad-core ARM Cortex-A9 MPCore.
• The main GPU, a PowerVR SGX543MP4+ by Imagination Technologies.
• Many accelerators (some proprietary, others off the shelf), including an ‘AVC Decoder’, DMA Controllers, a big DSP and security blocks (which includes hideed ROM space).
• Around 640 MB of RAM (split into multiple types).
• Last but not least, legacy PlayStation Portable circuitry (the MIPS CPU and the Graphics Engine).

…and thcdisesteemfulout this article we’ll get a see at each of those!

The main CPU

Our new study subject is the ARM Cortex-A9 MPCore, a very depfinishable processor from ARM Ltd. 

To create this study captivating and help understand all the technoreasonable better since my last analysis of the ARM11 CPU, I’d enjoy to begin with an supervise of the new ‘Cortex’ line. Then, a rapid see at the Cortex-A8 (the predecessor of the A9). Finpartner, the novelties of the Cortex-A9.

Continued history

ARM has come a lengthy way since the days of the Game Boy Advance, to recall its meaningful milestones:

The next accomplishment would become Cortex: a new brand carrying a changed teachion set and processor line. This time, ARM would adselect trains traditionpartner establish in the desktop/toilstation labelet, eventupartner coming heads-to-head with Intel’s x86. Curiously enough, Cortex’s labeleting strategy is very aenjoy to Intel’s Pentium, in the sense that the name ‘Cortex’ ultimately becomes an ambiguous term to hide the complicated identifications and variants of all its chips.

The Cortex line-up

With the declarement of Cortex as a brand, ARM’s product line diversified into three differentiateable sectors: industrial, percreateance and embedded. Thus, any Cortex CPU would be fitted into a ‘profile’ (Cortex-R, Cortex-A and Cortex-M, esteemively), each concentrateing one of these labelets. For this study, we’ll intensify on the Cortex-A line, which intensifyed on percreateance or ‘applications’ (in other words, participater devices); and made a proestablish impact on cleverphones.

ARM’s first deinhabitry for ‘applications’ was the Cortex-A8 CPU. It shipped in 2005, but it wasn’t until four years procrastinateedr that cleverphones begined adselecting it. The iPhone 3GS, Motorola Droid and Nokia N900 were its debuting flagship carriers. Be as it may, the CPU can’t toil by itself, so these devices relied on Samsung and Texas Instruments to package all the vital modules into a SoC (combining the CPU with the GPU, modem and other I/O).

It’s worth refering that the Cortex CPU was also a remendd choice for manufacturers finpartner making the jump from Intel’s XScale, such as RIM and its Bconciseageberry line. On the other side, brave cleverphones enjoy the Toshiba TG01 and the HTC HD2 only adselected Cortex’s technology partipartner (they carry out the same teachion set, but its microarchitecture was scheduleed by Qualcomm instead).

Notice that these devices also coincide with a brave time when participaters ponderably alterd their attitude towards cleverphones: these were initipartner supposeed for inmeaningful tasks such as text messages and e-mail, but now they were begining to provide access to prohibitk accounts, with only a scant years behind conveying concallous payments.

More news

Alengthy the Cortex-A8 came the ARMv7 teachion set. This is the continuation of the ARMv6 ISA by broadening its multi-processing and SIMD capabilities ^[3].

ARMv7 is the lengthyest-living 32-bit ISA from ARM, but also the last one. Its expansive-spread adselection would still be highly fragmented, mainly due to the split of Cortex into the aforerefered profiles (spawning contrastent subsets of the ISA), existing adselection of the ARMv6 (i.e. the first Raspberry Pi and Nokia’s Symbian platcreate only helped ARMv6) and the broadenment of Thumb. To elude making this topic too dense, I’ve pledgeted contrastent sections further down to talk these.

The core

So far I’ve talked about the Cortex-A8, that’s the first Cortex CPU. But the PSVita actupartner bundles the flourishing CPU, the Cortex-A9 (freed two years procrastinateedr, in 2007). It’s asking to see that this console was fair a scant months apart from the Nintfinisho 3DS, a console scheduleed with horizontal innovation in mind.

Moving on, the filled name of the PSVita’s CPU is ARM Cortex-A9 MPCore. Overall, this uncomfervents the CPU is a cluster made of multiple Cortex-A9 cores, four in this case. It runs at a clock speed of up to 500 MHz ^[4], an underwhelming number pondering contransient adselecters of the quad-core A9, such as the Samsung Galaxy S III, achieveed speeds of 1.4 GHz ^[5]. It’s possible that battery life was the main priority here. Nevertheless, clock speed is not the only remendd meabravement, the inner toilings of the CPU are as vital.

Speaking of which, the new cores split many characteristics with their predecessor, the Cortex-A8, which includes ^[6]:

• The next-generation teachion set called ARMv7-A, I elucidate more details further on.
• 64 KB of L1 cache which inherently trails the Harvard architecture. Consequently, it’s splitd into 32 KB for data and 32 KB for teachions.
  • Cache coherency among the cores is automaticpartner regulated by the Snoop Control Unit, previously featured in the ARM11MpCore.
• 2-publish superscalar: For the first time, ARM has bcdisesteemfult teachion-level parallelism. This uncomfervents that, as lengthy as there are no hazards, the CPU will try to percreate two teachions using two split pipelines. This increases the amount of teachions percreated per clock cycle. MIPS and SuperH bcdisesteemfult this a decade before, but the two suffered a rapid demise, so it’s now ARM’s turn to carry it forward.
• Dynamic branch prediction: The CPU now predicts the execution path by count oning on two pledgeted buffers while conveying teachions. The first awaits whether an upcoming teachion will be a branch, and the next buffer maps the previous flow of the program. Finpartner, the latter is participated to predict whether upcoming branches will be getn or not ^[7].
  • It’s worth refering that this unit only predicts branching teachions, leave outting other selectimisation techniques such as conditionals or the IT teachion… Maybe that’s a hint about the future of the ARM ISA.
• A Memory Management Unit (MMU) with a Translation Lookaside Buffer (TLB). This is already normal on most CPUs.
  • By the way, in the case of the Cortex brand, only the ‘Cortex-A’ profile includes this package (the ‘Cortex-R’ bundles an MPU instead and the ‘Cortex-M’ includes neither).
• TrustZone: A new security subsystem that inserts a unreasonableension to the privilege levels of the MMU. It’s carry outed on both the challengingware level (by segregating bparticipates between non-protected and protected peripherals) and the software level (by executing a secondary and isoprocrastinateedd operating system that regulates braveial data). The exceptional OS is called Trusted Execution Environment.
• NEON Media Processing Engine (MPE), a new co-processor that carries out vector and floating-point operations. We’ll dive more into it in the next sections.

Now, the Cortex-A9 (establish in the PSVita) betters the innovative schedule by utilizeing meaningful betterments ^[8]:

• Multi-core help. This is most evident by seeing at Sony’s choice of a quad-core package.
  • As a side remark, this also elucidates why portable devices enjoy the iPad 2 and iPhone 4s (both carrying an A9) regulated to debut a dual-core CPU.
• Out-Of-Order execution thcdisesteemful the participate of enroll renaming. This is a huge step for ARM in further scaling its Instruction level parallelism, pondering other chips enjoy PowerPC were forced to aprohibitdon it.
  • This will also have a proestablish effect on the evolution of the ARM teachion set. You will see this in a future analysis of the Nintfinisho Switch.
• A variable-length pipeline, between 8 and 11 stages depfinishing on the operation. The total number may also increase if execution persists in the multimedia co-processor (elucidateed in the next section).

Moreover, Sony customised the package by inserting one of ARM’s fortifys called Primejoin Level 2 Cache Controller alengthy with 2 MB of L2 cache splitd among all cores ^[9]. Primejoin is a pliable cache subsystem which can be programmed with contrastent types of cache associations, from honest mapping to 16-way. If you are asking, years procrastinateedr ARM renamed the Primejoin brand to ‘CoreLink’ ^[10].

The lengthenn-up ISA

The ARMv7 teachion set in the Cortex-A9 features a multitude of extensions. The meaningfulity of alters will be in the create of SIMD capabilities and multiprocessing, you’ll acunderstandledge this when we get a sealr see into the novelties of the ARMv7.

More accelerators

The most notable component of the Cortex-A9, in particular for the PSVita, is the Media Processing Engine (MPE). This is ARM’s new coprocessor for 3D applications. It’s been engineered in a very convoluted way, however, as it percreates two contrastent but roverdelighted teachion sets:

• The Vector Floating-Point v3 (VFPv3): A continuation of VFPv2 for floating-point capabilities. It’s IEEE-754 compliant and now extfinished to provide teachions enjoy VCVT (to convert between mended-point and floating-point cherishs) and VMOV (to transfer cherishs between the CPU and the FPU enroll file). This is collaborative since the VFP only understands 32-bit and 64-bit floating-point cherishs.
  • The exact variant included in the Cortex-A9 is called ‘VFPv3-D32’, uncomferventing it includes thirty-two 64-bit enrolls.
  • Even though this ISA comprises the word ‘vector’, ARMv7 deprecated the participate of the vector teachions and the Cortex-A9 includes none ^[13]. So much for being called a ‘vector FPU’…
• The NEONv1, also understandn as ‘ARMv7 Advanced SIMD’, is the authentic vector teachion set, enabling to run multiple scalars at once. NEON provides sixteen 128-bit enrolls, which can be also split into thirty-two 64-bit or 32-bit ‘virtual’ enrolls. The integers being rund may be as big as 64 bits, while floating-point types can’t outdo 32 bits.
  • It’s worth reminding that Sony’s predecessor vector unit provided the immense amount of 128 enrolls, albeit 32-bit instead. If we do the math, the Cortex-A9 MPCore regulates to suit that number. Although, only 16 enrolls are accessible per core, and forget about the matrix-type insertressing that made the VFPU exceptional and effective. On the radiant side, perhaps there’s a new selectimisation opportunity by having multiple cores compute SIMD teachions in parallel.

NEON and VFPv3 split the same enroll file, but they’re still pondered split ISAs. Considering ancestral processors enjoy the SH-4 deinhabitred SIMD operations by sshow extfinishing its FPU, one can only wonder why ARM finished up producing two contrastent ISAs. Well, the exscheduleation is basic: neither is feature-finish. Particularly, VFPv3 doesn’t help mended-point while NEON is not compliant with the IEEE 754 standard ^[14]. So, as an intersettle solution, the circuitry was segregated.

All in all, this uncomfervents the compiler will necessitate to toil challenginger selectimising the code, but it still creates you wonder why ARM’s engineers finished up complicating skinnygs to absurd levels. In my opinion, I apshow NEON was rushed to rapidly counter Wireless MMX (Intel’s proprietary SIMD extension for the XScale, freed a year before) as ARM didn’t finishelight seeing Intel bundling exclusive teachions only participateable on the XScale ^[15]. This is also complemented by the fact the official write downation on Cortex’s timings was hurried as well ^[16].

The master bus

Another famous product from ARM, the AMBA protocol scheduleed for intercombineing components, carries forward with the Cortex-A9. Still in its third revision, the AXI subset was picked for interfacing the cores and outer components outside the MPCore cluster. Curiously enough, it’s the same choice establish in the ARM11 and its well-understandn adselecter, the Nintfinisho 3DS.

Envisioning the future

After the Cortex-A9, the line of succession became increasingly confusing. The Cortex-A series was broken down into four more categories, ranging from the top percreateer to the most energy-effective. In doing so, the model numbering of each CPU became absurdly difficult to trail, but I guess it didn’t matter for the finish participater becaparticipate these CPUs weren’t sbetter off-the-shelf!

The next big milestone for ARM will debut in 2011, with the arrival of ARMv8. I’ll talk more about this in a future article about the Nintfinisho Switch.

Media coprocessors

Next to the ARM cluster, Sony bundled a couple of accelerators that help gaming-roverdelighted tasks. Just enjoy the previous Media Engine group, they are finishly proprietary and act as a bconciseage box. Programmers are not uncomferventt to fiddle with them honestly but thcdisesteemful the official SDK.

Memory participateable

Enough about CPU talk! Let’s now get a see at the memory bundled wiskinny the PSVita.

As it’s customary with portable consoles, there are multiple memory types in this system.

Main memory

To begin with, at the top of Kermit’s stack, we discover a big block that hoparticipates 512 MB of LPDDR2 SDRAM and is participated as the main toiling area. In case you are now wondering “I get the ‘512 MB’ part, but what’s with all those initials?”, you’re not alone.

There’s a lot of terminology to unpack here, let’s begin by fractureing down the ‘LPDDR2 SDRAM’ name into two groups, from right to left, and then checking what’s inside each:

1. SDRAM uncomfervents ‘Synchronous Dynamic RAM’.
   • Dynamic RAM (DRAM) is the opposite of ‘Static RAM’ (SRAM). DRAM is inexpensiveer to create but shows more procrastinateedncy. That’s why CPU cache is made of SRAM while outer ambiguous-purpose memory is made of DRAM.
   • Synchronous DRAM (SDRAM) uncomfervents transfers are synchronised on par with the CPU clock, improving its thcdisesteemfulput.
2. LPDDR2 uncomfervents ‘Low Power Double Data Rate 2’.
   • Double Data Rate (DDR) states that transfers encode twice the increateation per cycle.
   • Low Power (LP) is a novelty here. This is not normal DDR, but a contrastent variant called ‘Low Power’. It was initipartner imagined as a modification of DDR SDRAM, then became its own brand alengthyside others (as it happened with GDDR). While DDR betters to increase the prohibitdwidth, new revisions of LP intensify on reducing its operating voltage. As you may guess, its main adselecters are phones and laptops.
   • The ‘2’ at the finish signifies it’s the second revision of LPDDR. Its definiteation was published in 2009 and, among other betterments, it only necessitates 1.2 Volts to toil (appraised to 1.35 V for DDR3).

Other memory

There’s another big block of 128 MB of Cached DRAM (CDRAM) predominantly combineed to the GPU. CDRAM is yet-another type of RAM that fuses the traditional (and inexpensive/cataloglesser) DRAM with a bit of SRAM ^[23]. The latter acts as cache to speed up widespread memory access.

Last but not least, the SoC also fits 16 KB of SRAM, but it’s reserved for system functions ^[24]. You may want to understand that it’s the exact amount of SRAM also establish in the PlayStation Portable, you’ll soon see why.

One last CPU

Last but not least, there’s an insertitional CPU inside Kermit: The better MIPS32 4k (the same one bundled with the PlayStation Portable) ^[25]. The intention was to provide backwards compatibility with PlayStation Portable and PlayStation 1 games. That’s the one and only (official) participate for the MIPS CPU, with no co-processing capability in place.

Speaking of backwards compatibility, Kermit doesn’t include the Media Engine ^[26], although being a bconciseage box uncomfervents that the software doesn’t attfinish about what’s behind the scenes. Thus, the functions of that co-CPU are duplicated thcdisesteemful Venezia instead.

For the remaining I/O, MIPS is not physicpartner combineed to the rest of the challengingware, only the Cortex-A9 is. Thus, the PSP emulation software (running on the MIPS CPU) seeks services to the ARM CPU by follotriumphg a protocol called ‘Remote Procedure Call’ (RPC) ^{[27] [28]}.

Finpartner, 64 MB of CDRAM are also reserved for this service. Those 16 KB of SRAM are also spreadd to the PSP emulator ^[29], as innovative PSP games would predict to discover.

Next: Graphics

That’s it for now! In the next part we’ll get a see at VideoLogic’s evolution to become a directing GPU in the mobile labelet, culminating in their signature PowerVR MBX GPU. Stay tuned for the next deinhabitry!