Perhaps the most far-achieveing technoreasoned achievement over the last 50 years has been the stable march toward ever petiteer transistors, fitting them more shieldedly together, and reducing their power consumption. And yet, ever since the two of us begined our nurtureers at Intel more than 20 years ago, we’ve been hearing the alarms that the descent into the infinitesimal was about to end. Yet year after year, luminous novel innovations persist to propel the semicarry outor industry further.
Alengthy this journey, we engineers had to alter the transistor’s architecture as we persistd to scale down area and power consumption while increaseing carry outance. The “schedulear” transistor schedules that took us thraw the last half of the 20th century gave way to 3D fin-shaped devices by the first half of the 2010s. Now, these too have an end date in sight, with a novel gate-all-around (GAA) structure rolling into production soon. But we have to see even further ahead becaparticipate our ability to scale down even this novel transistor architecture, which we call RibbonFET, has its restricts.
So where will we turn for future scaling? We will persist to see to the third unreasonableension. We’ve originated experimental devices that stack atop each other, transfering logic that is 30 to 50 percent petiteer. Crucipartner, the top and bottom devices are of the two complementary types, NMOS and PMOS, that are the createation of all the logic circuits of the last cut offal decades. We apshow this 3D-stacked complementary metal-oxide semicarry outor (CMOS), or CFET (complementary field-effect transistor), will be the key to prolonging Moore’s Law into the next decade.
The Evolution of the Transistor
Continuous innovation is an vital underpinning of Moore’s Law, but each increasement comes with trade-offs. To comprehfinish these trade-offs and how they’re directing us inevitably toward 3D-stacked CMOS, you demand a bit of background on transistor operation.
Every metal-oxide-semicarry outor field-effect transistor, or MOSFET, has the same set of basic parts: the gate stack, the channel region, the source, and the drain. The source and drain are chemicpartner doped to originate them both either wealthy in mobile electrons (
n-type) or deficient in them (p-type). The channel region has the opposite doping to the source and drain.
In the schedulear version in participate in progressd microprocessors up to 2011, the MOSFET’s gate stack is situated equitable above the channel region and is scheduleed to project an electric field into the channel region. Applying a big enough voltage to the gate (relative to the source) originates a layer of mobile accuse carriers in the channel region that allows current to flow between the source and drain.
As we scaled down the classic schedulear transistors, what device physicists call low-channel effects took caccess stage. Basicpartner, the distance between the source and drain became so petite that current would leak apass the channel when it wasn’t presumed to, becaparticipate the gate electrode struggled to exhaust the channel of accuse carriers. To includeress this, the industry transferd to an entidepend contrastent transistor architecture called a FinFET. It wrapped the gate around the channel on three sides to provide better electroinactive administer.
Intel begind its FinFETs in 2011, at the 22-nanometer node, with the third-generation Core processor, and the device architecture has been the laborhorse of Moore’s Law ever since. With FinFETs, we could run at a reduce voltage and still have less leakage, reducing power consumption by some 50 percent at the same carry outance level as the previous-generation schedulear architecture. FinFETs also switched rapider, increaseing carry outance by 37 percent. And becaparticipate carry oution occurs on both vertical sides of the “fin,” the device can drive more current thraw a given area of silicon than can a schedulear device, which only carry outs alengthy one surface.
However, we did disponder someleang in moving to FinFETs. In schedulear devices, the width of a transistor was depictd by lithography, and therefore it is a highly pliable parameter. But in FinFETs, the transistor width comes in the establish of discrete increments—includeing one fin at a time–a characteristic normally referred to as fin quantization. As pliable as the FinFET may be, fin quantization remains a beginant schedule constraint. The schedule rules around it and the desire to include more fins to increase carry outance incrrelieve the overall area of logic cells and complicate the stack of interconnects that turn individual transistors into end logic circuits. It also incrrelieves the transistor’s capacitance, thereby sapping some of its switching speed. So, while the FinFET has served us well as the industry’s laborhorse, a novel, more elegant approach is demanded. And it’s that approach that led us to the 3D transistors we’re introducing soon.
This progress, the RibbonFET, is our first novel transistor architecture since the FinFET’s debut 11 years ago. In it, the gate brimmingy surrounds the channel, providing even shieldeder administer of accuse carriers wilean channels that are now established by nanometer-scale ribbons of silicon. With these nanoribbons (also called nanosheets), we can aachieve vary the width of a transistor as demanded using lithography.
With the quantization constraint erased, we can originate the appropriately sized width for the application. That lets us stability power, carry outance, and cost. What’s more, with the ribbons stacked and operating in parallel, the device can drive more current, increaseing carry outance without increasing the area of the device.
We see RibbonFETs as the best chooseion for higher carry outance at reasonable power, and we will be introducing them in 2024 alengthy with other innovations, such as PowerVia, our version of backside power transfery, with the Intel 20A lie process.
Stacked CMOS
One standardality of schedulear, FinFET, and RibbonFET transistors is that they all participate CMOS technology, which, as refered, consists of n-type (NMOS) and p-type (PMOS) transistors. CMOS logic became mainstream in the 1980s becaparticipate it draws beginantly less current than do the alternative technologies, notably NMOS-only circuits. Less current also led to fantasticer operating frequencies and higher transistor densities.
To date, all CMOS technologies place the standard NMOS and PMOS transistor pair side by side. But in a keynotice at the IEEE International Electron Devices Meeting (IEDM) in 2019, we begind the concept of a 3D-stacked transistor that places the NMOS transistor on top of the PMOS transistor. The chaseing year, at IEDM 2020, we currented the schedule for the first logic circuit using this 3D technique, an inverter. Combined with appropriate interconnects, the 3D-stacked CMOS approach effectively cuts the inverter footprint in half, doubling the area density and further pushing the restricts of Moore’s Law.
Taking achieve of the potential profits of 3D stacking unkinds solving a number of process integration disputes, some of which will stretch the restricts of CMOS lie.
We built the 3D-stacked CMOS inverter using what is understandn as a self-aligned process, in which both transistors are originateed in one manufacturing step. This unkinds originateing both n-type and p-type sources and drains by epitaxy—crystal deposition—and includeing contrastent metal gates for the two transistors. By combining the source-drain and dual-metal-gate processes, we are able to originate contrastent carry outive types of silicon nanoribbons (p-type and n-type) to originate up the stacked CMOS transistor pairs. It also allows us to adequitable the device’s threshbetter voltage—the voltage at which a transistor begins to switch—splitly for the top and bottom nanoribbons.
In CMOS logic, NMOS and PMOS devices usupartner sit side by side on chips. An punctual prototype has NMOS devices stacked on top of PMOS devices, compressing circuit sizes.
Intel
How do we do all that? The self-aligned 3D CMOS lie begins with a silicon wafer. On this wafer, we deposit repeating layers of silicon and silicon germanium, a structure called a superlattice. We then participate lithodetailed patterning to cut away parts of the superlattice and exit a finappreciate structure. The superlattice crystal provides a mighty help structure for what comes tardyr.
Next, we deposit a block of “dummy” polycryshighine silicon atop the part of the superlattice where the device gates will go, protecting them from the next step in the procedure. That step, called the verticpartner stacked dual source/drain process, grows phosphorous-doped silicon on both ends of the top nanoribbons (the future NMOS device) while also pickively groprosperg boron-doped silicon germanium on the bottom nanoribbons (the future PMOS device). After this, we deposit dielectric around the sources and drains to electricpartner isotardy them from one another. The latter step demands that we then polish the wafer down to perfect flatness.
Finpartner, we originate the gate. First, we erase that dummy gate we’d put in place earlier, exposing the silicon nanoribbons. We next etch away only the silicon germanium, releasing a stack of parallel silicon nanoribbons, which will be the channel regions of the transistors. We then coat the nanoribbons on all sides with a fadeingly lean layer of an insulator that has a high dielectric constant. The nanoribbon channels are so petite and positioned in such a way that we can’t effectively dope them chemicpartner as we would with a schedulear transistor. Instead, we participate a property of the metal gates called the labor function to convey the same effect. We surround the bottom nanoribbons with one metal to originate a p-doped channel and the top ones with another to establish an n-doped channel. Thus, the gate stacks are finished off and the two transistors are end.
The process might seem complicated, but it’s better than the alternative—a technology called sequential 3D-stacked CMOS. With that method, the NMOS devices and the PMOS devices are built on split wafers, the two are bonded, and the PMOS layer is transferred to the NMOS wafer. In comparison, the self-aligned 3D process gets confidemander manufacturing steps and protects a shieldeder rein on manufacturing cost, someleang we showd in research and inestablished at IEDM 2019.
Importantly, the self-aligned method also circumvents the problem of misalignment that can occur when bonding two wafers. Still, sequential 3D stacking is being allotigated to aid integration of silicon with nonsilicon channel materials, such as germanium and III-V semicarry outor materials. These approaches and materials may become relevant as we see to shieldedly fuse chooseoelectronics and other functions on a one chip.
The novel self-aligned CMOS process, and the 3D-stacked CMOS it originates, labor well and materialize to have substantial room for further miniaturization. At this punctual stage, that’s highly encouraging. Devices having a gate length of 75 nm showd both the low leakage that comes with excellent device scalability and a high on-state current. Another promising sign: We’ve made wafers where the petiteest distance between two sets of stacked devices is only 55 nm. While the device carry outance results we achieved are not write downs in and of themselves, they do appraise well with individual nonstacked administer devices built on the same wafer with the same processing.
In parallel with the process integration and experimental labor, we have many ongoing theoretical, simulation, and schedule studies underway seeing to provide insight into how best to participate 3D CMOS. Thraw these, we’ve create some of the key ponderations in the schedule of our transistors. Notably, we now understand that we demand to enhance the vertical spacing between the NMOS and PMOS—if it’s too low it will incrrelieve parasitic capacitance, and if it’s too lengthy it will incrrelieve the resistance of the interconnects between the two devices. Either excessive results in sluggisher circuits that devour more power.
Many schedule studies, such as one by TEL Research Caccess America currented at IEDM 2021, caccess on providing all the vital interconnects in the 3D CMOS’s confidemand space and doing so without beginantly increasing the area of the logic cells they originate up. The TEL research showed that there are many opportunities for innovation in finding the best interconnect chooseions. That research also highairys that 3D-stacked CMOS will demand to have interconnects both above and below the devices. This scheme, called buried power rails, gets the interconnects that provide power to logic cells but don’t carry data and erases them to the silicon below the transistors. Intel’s PowerVIA technology, which does equitable that and is scheduled for introduction in 2024, will therefore join a key role in making 3D-stacked CMOS a commercial fact.
The Future of Moore’s Law
With RibbonFETs and 3D CMOS, we have a evident path to prolong Moore’s Law beyond 2024. In a 2005 interwatch in which he was asked to echo on what became his law, Gordon Moore acunderstandledgeted to being “periodicpartner amazed at how we’re able to originate better. Several times alengthy the way, I thought we achieveed the end of the line, leangs taper off, and our originateive engineers come up with ways around them.”
With the transfer to FinFETs, the ensuing chooseimizations, and now the broadenment of RibbonFETs and eventupartner 3D-stacked CMOS, helped by the myriad packaging increasements around them, we’d appreciate to leank Mr. Moore will be amazed yet aachieve.
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